Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory, including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices (e.g., NAND, NOR, etc.) have developed into a popular source of non-volatile memory for a wide range of electronic applications. Non-volatile memory is memory that can retain its data values for some extended period without the application of power. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming (which is sometimes referred to as writing) of charge-storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.
A NAND flash memory device is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory devices is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series, source to drain, between a pair of select transistors, e.g., a source select transistor and a drain select transistor. Each source select transistor is connected to a source line, while each drain select transistor is connected to a data line, such as column bit line. A “column” refers to a group of memory cells that are commonly coupled to a local data line, such as a local bit line. It does not require any particular orientation or linear relationship, but instead refers to the logical relationship between memory cell and data line.
To meet the demand for higher capacity memories, designers continue to strive for increasing memory density (e.g., the number of memory cells in a given area of an integrated circuit die). One way to increase the density of memory devices is to form stacked memory arrays, e.g., often referred to as three-dimensional memory arrays.
The memory cells at a common location (e.g., at a common vertical level) in a stacked memory array, for example, may form a tier of memory cells. The memory cells in each tier might be coupled to one or more access lines, such as local access lines (e.g., local word lines), that are in turn selectively coupled to drivers by transistors, such as pass transistors. In some examples, the memory cells in each tier might be commonly coupled to a common assess line that might be referred to as an access plate.
Each access plate commonly coupled to a respective tier of memory cells may be coupled to a pass transistor by a routing line. For example, the pass transistors and routing lines coupled to the respective access plates might be under the stacked memory array. However, as the number of tiers, and thus the number of access plates, increases so does the number of pass transistors and routing lines. For example, the number of pass transistors and routing lines might increase until there is not enough room under stacked memory array to accommodate all of the pass transistors and routing lines, at which point the size of the stacked memory array might need to be increased to accommodate the extra pass transistors and routing lines thereunder.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternatives to existing pass transistor and/or routing circuitry configurations in memory devices with stacked memory arrays.